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max11100 16-bit, +5v, 200ksps adc with 10a shutdown 19-6046; rev 1; 1/12 ordering information appears at end of data sheet. general description the max11100 low-power, 16-bit analog-to-digital con - verter (adc) features a successive-approximation adc, automatic power-down, fast 1.1 f s wake-up, and a high- speed spi/qspi?/microwire?-compatible interface. the max11100 operates with a single +5v analog supply and features a separate digital supply, allowing direct interfacing with 2.7v to 5.25v digital logic. at the maximum sampling rate of 200ksps, the max11100 typically consumes 2.45ma. power consumption is typi - cally 12.25mw (v avdd = v dvdd = +5v) at a 200ksps (max) sampling rate. autoshutdown? reduces supply current to 140 f a at 10ksps and to less than 10 f a at reduced sampling rates.excellent dynamic performance and low power, com - bined with ease of use and small package size (10-pin f max ? and 12-bump wlp), make the max11100 ideal for battery-powered and data-acquisition applications or for other circuits with demanding power consumption and space requirements. applications motor controlindustrial process control industrial i/o modules data-acquisition systems thermocouple measurements accelerometer measurements portable- and battery-powered equipment features s 16-bit resolution, no missing codes s +5v single-supply operation s adjustable logic level (2.7v to 5.25v) s input voltage range: 0 to v ref s internal track-and-hold, 4mhz input bandwidth s spi/qspi/microwire-compatible serial interface s small 10-pin max and wlp packages s low power 2.45ma at 200ksps 140a at 10ksps 0.1a in power-down mode qspi is a trademark of motorola, inc.microwire is a registered trademark of national semiconductor corp. autoshutdown is a trademark and max is a registered trademark of maxim integrated products, inc. functional diagram for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/max11100.related ain track-and- hold 16-bit sar adc control dvdd dgnd cs agnd avdd ref dout sclk max11100 output buffer for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated?s website at www.maximintegrated.com. downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 2 maxim integrated avdd to agnd ....................................................... -0.3v to +6v dvdd to dgnd ....................................................... -0.3v to +6v dgnd to agnd ................................................... -0.3v to +0.3v ain, ref to agnd ............................... -0.3v to (v avdd + 0.3v) sclk, cs to dgnd ................................................. -0.3v to +6v dout to dgnd .................................... -0.3v to (v dvdd + 0.3v) maximum current into any pin ....................................... q 50ma continuous power dissipation (t a = +70 n c) f max (derate 5.6mw/ n c above +70 n c) ..................... 444mw wlp (derate 16.1mw/ n c above +70 n c)...... 1300mw (note 1) operating temperature range .......................... -40 n c to +85 n c maximum junction temperature ..................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature ( f max only; soldering, 10s) ............. +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratingsstresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v avdd = v dvdd = 4.75v to 5.25v, f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = 4.096v, c ref = 4.7 f f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) note 1: all wlp devices are 100% production tested at t a = +25 n c . specifications over temperature limits are guaranteed by design and characterization. parameter symbol conditions min typ max units dc accuracy (note 2)resolution 16 bits relative accuracy inl (note 3) -2 +2 lsb differential nonlinearity dnl -1 +2 lsb transition noise rms noise q 0.65 lsb rms offset error 0.1 1 mv gain error (note 4) q 0.002 q 0.01 %fsr offset drift 0.4 ppm/c gain drift (note 4) 0.2 ppm/c dynamic specifications (1khz sine wave, 4.096v p-p ) (note 2) signal-to-noise plus distortion sinad 86 91.5 db signal-to-noise ratio snr 87 91.7 db total harmonic distortion thd -106 -90 db spurious-free dynamic range sfdr 92 108 db full-power bandwidth -3db point 4 mhz full-linear bandwidth sinad > 86db 10 khz conversion rateconversion time t conv (note 5) 5 240 f s serial clock frequency f sclk 0.1 4.8 mhz aperture delay t ad 15 ns aperture jitter t aj < 50 ps sample rate f s f sclk /24 200 ksps track/hold acquisition time t acq 1.1 f s downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 3 maxim integrated electrical characteristics (continued)(v avdd = v dvdd = 4.75v to 5.25v, f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = 4.096v, c ref = 4.7 f f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) parameter symbol conditions min typ max units analog input (ain)input range v ain 0 v ref v input capacitance c ain 40 pf input leakage current sclk idle 0.01 10 f a external referenceinput-voltage range v ref 3.8 v avdd v input current i ref v ref = 4.096v, f sclk = 4.8mhz 60 150 f a v ref = 4.096v, sclk idle 0.01 10 cs = dvdd, sclk idle 0.01 digital inputs (sclk, cs ) input high voltage v ih v dvdd = 2.7v to 5.25v 0.7 x v dvdd v input low voltage v il v dvdd = 2.7v to 5.25v 0.3 x v dvdd v input leakage current i in v in = 0 to v dvdd q 0.1 q 1 f a input hysteresis v hyst 0.2 v input capacitance c in 15 pf digital output (dout)output high voltage v oh i source = 0.5ma, v dvdd = 2.7v to 5.25v v dvdd - 0.25 v output low voltage v ol i sink = 2ma, v dvdd = 2.7v to 5.25v 0.4 v three-state output leakage current i l cs = dvdd q 0.1 q 10 f a three-state output capacitance c out cs = dvdd 15 pf power suppliesanalog supply v avdd 4.75 5.25 v digital supply v dvdd 2.7 5.25 v analog supply current i avdd cs = dgnd, 200ksps 1.85 2.5 ma digital supply current i dvdd cs = dgnd, dout = all zeros, 200ksps 0.6 1.0 ma shutdown supply current i avdd + i dvdd cs = dvdd, sclk = idle 0.1 10 f a power-supply rejection ratio psrr v avdd = v dvdd = 4.75v to 5.25v, full- scale input (note 6) 68 db downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 4 maxim integrated timing characteristics( v avdd = v dvdd = 4.75v to 5.25v , f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = 4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (see figure 1 , figure 2 , figure 3 , and figure 6 .) timing characteristics (v avdd = 4.75v to 5.25v, v dvdd = 2.7v to 5.25v , f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = 4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (see figure 1 , figure 2 , figure 3 , and figure 6 .) note 2: v avdd = v dvdd = +5v. note 3: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 4: offset and reference errors nulled. note 5: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: defined as the change in positive full scale caused by a q 5% variation in the nominal supply voltage. parameter symbol conditions min typ max units acquisition time t acq 1.1 f s sclk to dout valid t do c dout = 50pf 50 ns cs fall to dout enable t dv c dout = 50pf 80 ns cs rise to dout disable t tr c dout = 50pf 80 ns cs pulse width t csw 50 ns cs fall to sclk rise setup t css 100 ns cs rise to sclk rise hold t csh 0 ns sclk high pulse width t ch 65 ns sclk low pulse width t cl 65 ns sclk period t cp 208 ns parameter symbol conditions min typ max units acquisition time t acq 1.1 f s sclk to dout valid t do c dout = 50pf 100 ns cs fall to dout enable t dv c dout = 50pf 100 ns cs rise to dout disable t tr c dout = 50pf 80 ns cs pulse width t csw 50 ns cs fall to sclk rise setup t css 100 ns cs rise to sclk rise hold t csh 0 ns sclk high pulse width t ch 65 ns sclk low pulse width t cl 65 ns sclk period t cp 208 ns downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 5 maxim integrated typical operating characteristics (v avdd = v dvdd = 5v, f sclk = 4.8mhz, c load = 50pf, c ref = 4.7 f f, v ref = 4.096v, t a = +25 n c, unless otherwise noted.) differential nonlinearity (dnl) vs. code max11100 toc02 output code (decimal) dnl (lsb) 49152 32768 57344 40960 24576 16384 8192 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 65536 integral nonlinearity (inl) vs. code max11100 toc01 output code (decimal) inl (lsb) 49152 32768 57344 40960 24576 16384 8192 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 65536 inl and dnl vs. analog supply voltage max11100 toc03 v avdd (v) inl and dnl (lsb) 5.15 5.05 4.95 4.85 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 4.75 5.25 max inl max dnl min inl min dnl max11100 fft max11100 toc05 frequency (khz) 90 80 70 60 50 40 30 20 10 0 100 -120 -100 -80 -60 -40 -20 0 -140 magnitude (db) sinad vs. frequency max11100 toc06 frequency (khz) sinad (db) 10 1 10 20 30 40 50 60 70 80 90 100 0 0 100 inl and dnl vs. temperature max11100 toc04 temperature (c) inl and dnl (lsb) 60 35 10 -15 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 -40 85 max inl max dnl min inl min dnl sfdr vs. frequency max11100 toc07 frequency (khz) sfdr (db) 10 1 0.1 100 10 20 30 40 50 60 70 80 90 100 110 120 0 total harmonic distortion vs. frequency max11100 toc08 thd (db) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 frequency (khz) 10 1 0 100 downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 6 maxim integrated typical operating characteristics (continued) (v avdd = v dvdd = 5v, f sclk = 4.8mhz, c load = 50pf, c ref = 4.7 f f, v ref = 4.096v, t a = +25 n c, unless otherwise noted.) supply current vs. temperature max11100 toc11 supply current (ma) 0.5 1.0 1.5 2.0 2.5 0 temperature (c) 60 35 10 -15 -40 85 i dvdd i avdd analog supply current vs. supply voltage max11100 toc10 i avdd (ma) 1.82 1.84 1.86 1.88 1.901.80 v avdd (v) 5.15 5.05 4.95 4.85 4.75 5.25 shutdown supply current vs. temperature max11100 toc13 temperature (c) shutdown supply current (na) 60 35 10 -15 -40 85 5025 100 75 150125 0 offset error vs. analog supply voltage max11100 toc14 offset error (v) -300 -100 100 300 500 -500 v avdd (v) 5.15 5.05 4.95 4.85 4.75 5.25 shutdown supply current vs. supply voltage max11100 toc12 i shdn (na) supply voltage (v) 5.15 5.05 4.95 4.85 4.75 5.25 0 42 86 1210 14 1816 20 sample rate (ksps) 100 10 0.0010 0.0100 0.1000 1.0000 10.0000 0.0001 1 1000 supply current vs. sample rate max11100 toc09 supply current (ma) i avdd i dvdd downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 7 maxim integrated typical operating characteristics (continued) (v avdd = v dvdd = 5v, f sclk = 4.8mhz, c load = 50pf, c ref = 4.7 f f, v ref = 4.096v, t a = +25 n c, unless otherwise noted.) signal-to-noise ratio (snr) and signal-to-noise and distortion ratio (sinad) vs. temperature max11100 toc18 snr and sinad (db) 91.0 91.5 92.0 92.5 93.090.5 temperature (c) 60 35 10 -15 -40 85 sinad snr f in = 1khz gain error vs. analog supply voltage max11100 toc16 gain error (%fs) -0.006 -0.002 0.002 0.006 0.010 -0.010 v avdd (v) 5.15 5.05 4.95 4.85 4.75 5.25 gain error vs. temperature max11100 toc17 gain error (%fs) -0.006 -0.002 0.002 0.006 0.010 -0.010 temperature (c) 60 35 10 -15 -40 85 offset error vs. temperature max11100 toc15 offset error (v) -300 -100 100 300 500 -500 temperature (c) 60 35 10 -15 -40 85 downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 8 maxim integrated pin configurations pin description pin name function wlp max a1, b2 6 ref external reference voltage input. sets the analog voltage range. bypass to agnd with a 4.7 f f capacitor. a2 7 avdd analog +5v supply voltage. bypass to agnd with a 0.1 f f capacitor. a3, b1, c2 4, 8 agnd analog ground a4 10 sclk serial clock input. sclk drives the conversion process and clocks out data at data rates up to 4.8mhz. b3 2 dgnd digital ground b4 9 cs active-low chip-select input. forcing cs high places the max11100 shutdown with a typical current of 0.1 f a. a high-to-low transition on cs activates normal operating mode and initiates a conversion. c1 5 ain analog input c3 3 dvdd digital supply voltage. bypass to dgnd with a 0.1 f f capacitor. c4 1 dout serial data output. data changes state on sclk?s falling edge. dout is high impedance when cs is high. max11100 top view + max 2 dgnd 1 dout dvdd 3 agnd ain cs sclkagnd avdd ref 4 5 9 10 8 7 6 max11100 top view (bump side down) wlp dout ain cs agnd sclk ref + 1 2 34 a agnd dvdd ref dgnd avdd agnd b c downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 9 maxim integrated detailed description the max11100 includes an input track-and-hold (t/h) and successive-approximation register (sar) circuitry to convert an analog input signal to a digital 16-bit output. figure 4 shows the max11100 in its simplest configura - tion. the serial interface requires only three digital lines (sclk, cs , and dout) and provides an easy interface to microprocessors ( f ps). the max11100 has two power modes: normal and shut - down. driving cs high places the max11100 in shut - down, reducing the supply current to 0.1 f a (typ), while pulling cs low places the max11100 in normal operating mode. falling edges on cs initiate conversions that are driven by sclk. the conversion result is available at dout in unipolar serial format. the serial data stream consists of eight zeros followed by the data bits (msb first). figure 3 shows the interface timing diagram. analog input figure 5 illustrates the input sampling architecture of the adc. the voltage applied at ref sets the full-scale input voltage. track-and-hold (t/h) in track mode, the analog signal is acquired on the inter - nal hold capacitor. in hold mode, the t/h switches open and the capacitive dac samples the analog input. figure 1. load circuits for dout enable time and sclk to dout delay time figure 2. load circuits for dout disable timefigure 3. detailed serial interface timing dout a) v ol to v oh b) high-z to v ol and v oh to v ol dout 1ma 1ma dgnd dgnd c load = 50pf c load = 50pf v dd dout a) v oh to high-z b) v ol to high-z dout 1ma 1ma dgnd dgnd c load = 50pf c load = 50pf v dd sclk dout t css t ch t cl t dv t csh t csw t tr t do t cp cs downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 10 maxim integrated during the acquisition, the analog input (ain) charges capacitor cdac. the acquisition interval ends on the falling edge of the sixth clock cycle ( figure 6 ). at this instant, the t/h switches open. the retained charge on cdac represents a sample of the input. in hold mode, the capacitive digital-to-analog converter (dac) adjusts during the remainder of the conversion cycle to restore node zero to zero within the limits of 16-bit resolution. at the end of the conversion, force cs high and then low to reset the input side of the cdac switches back to ain, and charge cdac to the input signal again. the time required for the t/h to acquire an input sig - nal is a function of how quickly its input capacitance is charged. if the input signal?s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the maximum time the device takes to acquire the signal. use the following formula to calculate acquisi - tion time: t acq = 13(r s + r in ) x 35pf where r in = 800 i , r s = the input signal?s source impedance, and t acq is never less than 1.1 f s. a source impedance less than 1k i does not significantly affect the adc?s performance.to improve the input signal bandwidth under ac condi - tions, drive ain with a wideband buffer (> 4mhz) that can drive the adc?s input capacitance and settle quickly. input bandwidth the adc?s input tracking circuitry has a 4mhz small- signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc?s sampling rate by using undersampling techniques. to avoid aliasing of unwant - ed high-frequency signals into the frequency band of interest, use anti-alias filtering. analog input protection internal protection diodes, which clamp the analog input to avdd or agnd, allow the input to swing from v agnd - 0.3v to v avdd + 0.3v, without damaging the device. if the analog input exceeds 300mv beyond the supplies, limit the input current to 10ma. digital interface initialization after power-up and starting a conversion the digital interface consists of two inputs, sclk and cs , and one output, dout. a logic-high on cs places the max11100 in shutdown (autoshutdown) and places dout in a high-impedance state. a logic-low on cs places the max11100 in the fully powered mode.to start a conversion, pull cs low. a falling edge on cs initiates an acquisition. sclk drives the a/d conversion and shifts out the conversion results (msb first) at dout. timing and control conversion-start and data-read operations are con - trolled by the cs and sclk digital inputs ( figure 6 and figure 7 ). ensure that the duty cycle on sclk is between 40% and 60% at 4.8mhz (the maximum clock frequency). for lower clock frequencies, ensure that the minimum high and low times are at least 65ns. conversions with sclk rates less than 100khz can result in reduced accuracy due to leakage. note: coupling between sclk and the analog inputs (ain and ref) may result in an offset. figure 4. typical operating circuit figure 5. equivalent input circuit sclk dout agnd dgnd ain ref avdd dvdd dout sclk cs ain v ref +5v +5v 4.7f 0.1f 0.1f gnd max11100 cs c dac 32pf r in 800 hold hold c switch 3pf ain ref gnd zero capacitive dac autozero rail track track downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 11 maxim integrated variations in frequency, duty cycle, or other aspects of the clock signal?s shape result in changing offset. a cs falling edge initiates an acquisition sequence. the analog input is stored in the capacitive dac, dout changes from high impedance to logic-low, and the adc begins to convert after the sixth clock cycle. sclk drives the conversion process and shifts out the conversion result on dout. sclk begins shifting out the data (msb first) after the fall - ing edge of the 8th sclk pulse. twenty-four falling clock edges are needed to shift out the eight leading zeros and 16 data bits. extra clock pulses occurring after the conversion result has been clocked out, and prior to the rising edge of cs , produce trailing zeros at dout and have no effect on the converter operation.force cs high after reading the conversion?s lsb to reset the internal registers and place the max11100 in shutdown. for maximum throughput, force cs low again to initiate the next conversion immediately after the speci - fied minimum time (t csw ). note: forcing cs high in the middle of a conversion immediately aborts the conversion and places the max11100 in shutdown. figure 6. external timing diagramfigure 7. shutdown sequence cs sclk 20 16 24 12 14 8 6 dout d15 d14 d13 d12 d11 d10 d9 d1 d0 d8 d5 d4 d3 d2 d7 d6 t csh t tr t do t acq t css t ch t cl t dv complete conversion sequence conversion 0 conversion 1 powered up powered up powered down dout cs timing not to scale. downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 12 maxim integrated output coding and transfer function the data output from the max11100 is binary and figure 8 depicts the nominal transfer function. code transitions occur halfway between successive-integer lsb values (v ref = 4.096v and 1 lsb = 63 f v or 4.096v/65536). applications information external reference the max11100 requires an external reference with a +3.8v and avdd voltage range. connect the external reference directly to ref. bypass ref to agnd with a 4.7 f f capacitor. when not using a low-esr bypass capacitor, use a 0.1 f f ceramic capacitor in parallel with the 4.7 f f capacitor. noise on the reference degrades conversion accuracy.the input impedance at ref is 40k i for dc currents. during a conversion the external reference at ref must deliver 100 f a of dc load current and have an output impedance of 10 i or less. for optimal performance, buffer the reference through an op amp and bypass the ref input. consider the max11100?s equivalent input noise (38 f v rms ) when choosing a reference. input buffer most applications require an input buffer amplifier to achieve 16-bit accuracy. if the input signal is multiplexed, switch the input channel immediately after acquisition, rather than near the end of or after a conversion ( figure 9 ). this allows the maximum time for the input buffer ampli - fier to respond to a large step change in the input signal. the input amplifier must have a slew rate of at least 2v/ f s to complete the required output-voltage change before the beginning of the acquisition time. at the beginning of the acquisition, the internal sam - pling capacitor array connects to ain (the amplifier output), causing some output disturbance. ensure that the sampled voltage has settled before the end of the acquisition time. digital noise digital noise can couple to ain and ref. the conversion clock (sclk) and other digital signals active during input acquisition contribute noise to the conversion result. noise signals synchronous with the sampling interval result in an effective input offset. asynchronous signals produce random noise on the input, whose high-frequen - cy components can be aliased into the frequency band of interest. minimize noise by presenting a low imped - ance (at the frequencies contained in the noise signal) at the inputs. this requires bypassing ain to agnd, or buffering the input with an amplifier that has a small- signal bandwidth of several mhz, or preferably both. ain has 4mhz (typ) of bandwidth. distortion avoid degrading dynamic performance by choosing an amplifier with distortion much less than the max11100?s total harmonic distortion (thd = -102db at 1khz) at frequencies of interest. if the chosen amplifier has insufficient common-mode rejection, which results in degraded thd performance, use the inverting configu - ration (positive input grounded) to eliminate errors from this source. low temperature-coefficient, gain-setting resistors reduce linearity errors caused by resistance changes due to self-heating. to reduce linearity errors due to finite amplifier gain, use amplifier circuits with suf - ficient loop gain at the frequencies of interest. dc accuracy to improve dc accuracy, choose a buffer with an offset much less than the max11100?s offset (1mv (max) for +5v supply), or whose offset can be trimmed while main - taining stability over the required temperature range. figure 8. unipolar transfer function, full scale (fs) = v ref , zero scale (zs) = gnd output code full-scale transition 11 . . . 11111 . . . 110 11 . . . 101 00 . . . 01100 . . . 010 00 . . . 001 00 . . . 000 12 3 0 fs fs - 3/2 lsb fs = v ref input voltage (lsb) 1 lsb = v ref 65536 downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 13 maxim integrated figure 9. change multiplexer input near beginning of conversion to allow time for slewing and settling serial interfaces the max11100?s interface is fully compatible with spi, qspi, and microwire standard serial interfaces. if a serial interface is available, establish the cpu?s serial interface as master, so that the cpu generates the serial clock for the max11100. select a clock frequency between 100khz and 4.8mhz: 1) use a general-purpose i/o line on the cpu to pull cs low. 2) activate sclk for a minimum of 24 clock cycles. the serial data stream of eight leading zeros followed by the msb of the conversion result begins at the fall - ing edge of cs . dout transitions on sclk?s falling edge and the output is available in msb-first format. observe the sclk to dout valid timing characteris - tic. clock data into the f p on sclk?s rising edge. 3) pull cs high at or after the 24th falling clock edge. if cs remains low, trailing zeros are clocked out after the least significant bit (d0 = lsb). 4) with cs high, wait at least 50ns (t csw ) before start - ing a new conversion by pulling cs low. a conver - sion can be aborted by pulling cs high before the conversion ends. wait at least 50ns before starting a new conversion. a0a1 clk change mux input here conversion in1 a0 a1 in2in3 in4 out acquisition 4-to-1 mux ain cs max11100 cs downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 14 maxim integrated data can be output in three 8-bit sequences or con - tinuously. the bytes contain the results of the conversion padded with eight leading zeros before the msb. if the serial clock has not been idled after the lsb (d0) and cs has been kept low, dout sends trailing zeros. spi and microwire interfaces when using the spi ( figure 10a ) or microwire ( figure 10b ) interfaces, set cpol = 0 and cpha = 0. conversion begins with a falling edge on cs ( figure 10c ). three con - secutive 8-bit readings are necessary to obtain the entire 16-bit result from the adc. dout data transitions on the serial clock?s falling edge. the first 8-bit data stream contains all leading zeros. the second 8-bit data stream contains the msb through d8. the third 8-bit data stream contains d7 through d0. figure 10c. spi/microwire interface timing sequence (cpol = cpha = 0) figure 10a. spi connections figure 10b. microwire connections dout* cs sclk 1st byte read 2nd byte read *when cs is high, dout = high-z msb high-z 3rd byte read lsb d1 d0 d7 d6 d5 d4 d3 d2 24 20 16 12 8 6 4 1 d15 d14 d13 d12 d11 d10 d9 d8 d7 0 00 00 00 0 timing not to scale. sclkdout i/o sck miso spi v dd ss max11100 cs max11100 cs microwire sclkdout i/o sk si downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 15 maxim integrated figure 11a. qspi connectionsfigure 11b. qspi interface timing sequence (cpol = cpha = 0) qspi interface using the high-speed qspi interface with cpol = 0 and cpha = 0, the max11100 supports a maximum f sclk of 4.8mhz. figure 11a shows the max11100 connected to a qspi master and figure 11b shows the associated interface timing. pic16 with ssp module and pic17 interface the max11100 is compatible with a pic16/pic17 micro - controller ( f c) using the synchronous serial-port (ssp) module.to establish spi communication, connect the controller as shown in figure 12a . configure the pic16/pic17 as system master, by initializing its synchronous serial-port control register (sspcon) and synchronous serial-port status register (sspstat) to the bit patterns shown in table 1 and table 2 . in spi mode, the pic16/pic17 f c allows 8 bits of data to be synchronously transmitted and received simultane - ously. three consecutive 8-bit readings ( figure 12b ) are necessary to obtain the entire 16-bit result from the adc. dout data transitions on the serial clock?s falling edge and is clocked into the f c on sclk?s rising edge. the first 8-bit data stream contains all zeros. the second 8-bit data stream contains the msb through d8. the third 8-bit data stream contains bits d7 through d0. figure 12a. spi interface connection for a pic16/pic17 cs qspi sclkdout cs sck miso v dd ss max11100 dout* cs sclk *when cs is high, dout = high-z msb 20 16 d15 d14 d13 d12 d11 d10 d9 high-z d1 d0 24 12 14 8 6 d8 d5 d4 d3 lsb d7 d6 end of acquisition d2 scksdi gnd pic16/17 i/o sclk dout cs v dd v dd max11100 downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 16 maxim integrated table 1. detailed sspcon register contentstable 2. detailed sspstat register contents figure 12b. spi interface timing with pic16/pic17 in master mode (cke = 1, ckp = 0, smp = 0, sspm3 - sspm0 = 0001) control bit max11100 settings synchronous serial-port control register (sspcon) wcol bit 7 x write collision detection bit sspov bit 6 x receive overflow detect bit sspen bit 5 1 synchronous serial-port enable bit:0: disables serial port and configures these pins as i/o port pins. 1: enables serial port and configures sck, sdo, and sci pins as serial port pins. ckp bit 4 0 clock polarity select bit. ckp = 0 for spi master mode selection. sspm3 bit 3 0 synchronous serial-port mode select bit. sets spi master mode and selects f clk = f osc /16. sspm2 bit 2 0 sspm1 bit 1 0 sspm0 bit 0 1 control bit max11100 settings synchronous serial-port control register (sspstat) smp bit 7 0 spi data input sample phase. input data is sampled at the middle of the data output time. cke bit 6 1 spi clock edge select bit. data is transmitted on the rising edge of the serial clock. d/a bit 5 x data address bit p bit 4 x stop bit s bit 3 x start bit r/w bit 2 x read/write bit information ua bit 1 x update address bf bit 0 x buffer full status bit dout* cs sclk 1st byte read 2nd byte read *when cs is high, dout = high-z msb high-z 3rd byte read lsb d1 d0 d7 d6 d5 d4 d3 d2 24 20 16 12 d15 d14 d13 d12 d11 d10 d9 d8 0 00 00 00 0 d7 timing not to scale. downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 17 maxim integrated definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-fit straight line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nulled. the static linearity parameters for the max11100 are measured using the endpoint method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of 1 lsb guarantees no missing codes and a monotonic transfer function. aperture definitions aperture jitter (t aj ) is the sample-to-sample variation in the time between samples. aperture delay (t ad ) is the time between the falling edge of the sampling clock and the instant when the actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quantiza - tion error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quantiza - tion noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency?s rms amplitude to the rms equivalent of all the other adc output signals, excluding the dc offset. ( ) rms rms signal sinad(db) 20 log noise distortion ?? = ?? + ???? effective number of bits effective number of bits (enob) indicate the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc error consists of quantiza - tion noise only. with an input range equal to the full-scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76)/6.02 figure 13 shows the effective number of bits as a function of the max11100?s input frequency. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: 2222 2345 1 vvvv thd 20 log v ?? +++ ?? = ?? ?? ?? where v 1 is the fundamental amplitude and v 2 through v 5 are the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest fre - quency component. figure 13. effective number of bits vs. input frequency input frequency (khz) effective number of bits 10 1 2 4 6 8 10 12 14 16 0 0.1 100 downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 18 maxim integrated supplies, layout, grounding, and bypassing use pcbs with separate analog and digital ground planes. do not use wire-wrap boards. connect the two ground planes together at the max11100. isolate the digital supply from the analog with a low-value resistor (10 i ) or ferrite bead when the analog and digital sup - plies come from the same source ( figure 14 ). constraints on sequencing the power supplies and inputs are as follows: u apply agnd before dgnd. u apply ain and ref after avdd and agnd are present. u dvdd is independent of the supply sequencing. ensure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. a 5ma current flowing through a pcb ground trace impedance of only 0.05 i creates an error voltage of about 250 f v, 4 lsb error with a +4v full-scale system.the board layout should ensure that digital and analog signal lines are kept separate. do not run analog and dig - ital (especially the sclk and dout) lines parallel to one another. if one must cross another, do so at right angles. the adcs high-speed comparator is sensitive to high- frequency noise on the avdd power supply. bypass an excessively noisy supply to the analog ground plane with a 0.1 f f capacitor in parallel with a 1 f f to 10 f f low-esr capacitor. keep capacitor leads short for best supply- noise rejection. ordering information chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. figure 14. powering avdd and dvdd from a single supply + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package max11100eub+ -40 n c to +85 n c 10 f max MAX11100EWC+ -40 n c to +85 n c 12 wlp package type package code outline no. land pattern no. 10 f max u10+2 21-0061 90-0330 12 wlp w121a2+1 21-0009 refer to application note 1891 sclk dout agnd dgnd ain 10 ref avdd dvdd dout sclk cs ain v ref +5v 4.7f 0.1f 0.1f gnd max11100 cs downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 19 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/11 initial release ? 1 1/12 revised the absolute maximum ratings and electrical characteristics . 2?4 downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 20 maxim integrated downloaded from: http:///
max11100 16-bit, +5v, 200ksps adc with 10a shutdown 21 maxim integrated downloaded from: http:///

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